1. Field of the Invention
The present invention relates to semiconductor technologies, and more specifically, to metal-oxide-semiconductor (MOS) transistors having an extended drain structure and fabrication method thereof.
2. Description of the Related Art
In semiconductor devices, MOS transistors having an extended drain structure have been developed to improve a breakdown voltage of the conventional transistors. The extended drain MOS transistors are widely used for high power devices.
Referring to FIG. 1, the conventional extended drain MOS transistor is explained in terms of its structure and fabrication method. In FIG. 1, an N-channel MOS transistor is shown.
Dopants of a first conductivity type (e.g., boron) are injected into a silicon semiconductor substrate 10 to form a P well 12. Then, a shallow trench isolation is formed to define field and active regions. In the active regions where electronic circuitries including MOS transistors are to be formed, a gate oxide and polysilicon are sequentially deposited on the substrate 10. Through a photolithographic process, the gate oxide and polysilicon are patterned to form a gate stack consisted of a gate insulating layer 14 and a gate electrode 16.
With the gate electrode 16 as a mask, the dopants having lower density and opposite charge to the P-channel well 12 (e.g., phosphorous or arsenic) are injected into the substrate to form lightly doped source region 22a and light doped drain region (LDD region) 24a. 
After forming the regions 22a and 24a, insulating material is formed on the entire surface of the substrate 10 by low pressure chemical vapor deposition (LPCVD) and the deposited insulating material is selectively etched to leave material at the sidewalls of the gate electrode 16. The remaining insulating material forms a sidewall spacer 18 that enables the self-aligned process of the heavily doped drain region and electrically separates the gate electrode from the source/drain regions in subsequent salicide process.
With the gate electrode 16 and the sidewall spacer 18 as a mask, dopants having higher density and opposite charge to the P-channel well 12 (e.g., phosphorous or arsenic) are injected into the substrate 10 to form source/drain regions 22 and 24. In this process, a photoresist pattern (PR1) is used as shown in FIG. 1 to form an extended drain structure. The photoresist pattern (PR1) covers parts of the gate electrode 16 and drain region, and extends, in a horizontal direction on the substrate, to a predetermined distance, g, from the edge of the sidewall spacer 18 near to the drain region. As a result, the highly doped drain region 24 is formed to be distant by distance, g, from the gate electrode 16.
As explained above, the conventional extended drain MOS transistor has the highly doped drain region 24 remote from the gate polysilicon 16 for obtaining a breakdown voltage required by a design rule. However, the integration of the MOS transistor in a horizontal direction is degraded as the distance between the highly doped drain region and the gate electrode increases.